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| 32 Mbit (x16) Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B SST39VF640xB2.7V 64Mb (x16) MPF+ memories Data Sheet FEATURES: * Organized as 2M x16 * Single Voltage Read and Write Operations - 2.7-3.6V * Superior Reliability - Endurance: 100,000 Cycles (Typical) - Greater than 100 years Data Retention * Low Power Consumption (typical values at 5 MHz) - Active Current: 6 mA (typical) - Standby Current: 4 A (typical) - Auto Low Power Mode: 4 A (typical) * Hardware Block-Protection/WP# Input Pin - Top Block-Protection (top 32 KWord) for SST39VF3202B - Bottom Block-Protection (bottom 32 KWord) for SST39VF3201B * Sector-Erase Capability - Uniform 2 KWord sectors * Block-Erase Capability - Uniform 32 KWord blocks * Chip-Erase Capability * Erase-Suspend/Erase-Resume Capabilities * Hardware Reset Pin (RST#) * Security-ID Feature - SST: 128 bits; User: 128 words * Fast Read Access Time: - 70 ns * Latched Address and Data * Fast Erase and Word-Program: - Sector-Erase Time: 18 ms (typical) - Block-Erase Time: 18 ms (typical) - Chip-Erase Time: 35 ms (typical) - Word-Program Time: 7 s (typical) * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Toggle Bits - Data# Polling * CMOS I/O Compatibility * JEDEC Standard - Flash EEPROM Pin Assignments * Packages Available - 48-lead TSOP (12mm x 20mm) - 48-ball TFBGA (6mm x 8mm) * All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST39VF320xB devices are 2M x16 CMOS MultiPurpose Flash Plus (MPF+) manufactured with SST's proprietary, high-performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39VF320xB write (Program or Erase) with a 2.7-3.6V power supply. These devices conform to JEDEC standard pin assignments for x16 memories. Featuring high performance Word-Program, the SST39VF320xB devices provide a typical Word-Program time of 7 sec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, these devices are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. The SST39VF320xB devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 1 they significantly improve performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet high-density, surface mount requirements, the SST39VF320xB devices are offered in 48-lead TSOP and 48-ball TFBGA packages. See Figure 2 and Figure 3 for pin assignments. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet Device Operation Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. The SST39VF320xB also have the Auto Low Power mode which puts the device in a near standby mode after data has been accessed with a valid Read operation. This reduces the IDD active read current from typically 9 mA to typically 4 A. The Auto Low Power mode reduces the typical IDD active read current to the range of 2 mA/MHz of Read cycle time. The device exits the Auto Low Power mode with any address transition or control signal transition used to initiate another Read cycle, with no access time penalty. Note that the device does not enter Auto-Low Power mode after power-up with CE# held steadily low, until the first address transition or CE# is driven high. Any commands issued during the internal Program operation are ignored. During the command sequence, WP# should be statically held high or low. Sector/Block-Erase Operation The Sector- (or Block-) Erase operation allows the system to erase the device on a sector-by-sector (or block-byblock) basis. The SST39VF320xB offer both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (50H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (30H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (50H or 30H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-ofErase operation can be determined using either Data# Polling or Toggle Bit methods. See Figure 11 and Figure 12 for timing waveforms and Figure 25 for the flowchart. Any commands issued during the Sector- or Block-Erase operation are ignored. When WP# is low, any attempt to Sector(Block-) Erase the protected block will be ignored. During the command sequence, WP# should be statically held high or low. Read The Read operation of the SST39VF320xB is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 5). Erase-Suspend/Erase-Resume Commands The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode typically within 10 s after the Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erase-suspended sectors/blocks will output DQ2 toggling and DQ6 at `1'. While in Erase-Suspend mode, a Word-Program operation is allowed except for the sector or block selected for Erase-Suspend. To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue Erase Resume command. The operation is executed by issuing one byte command sequence with Erase Resume command (30H) at any address in the last Byte sequence. Word-Program Operation The SST39VF320xB are programmed on a word-by-word basis. Before programming, the sector where the word exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed within 10 s. See Figure 6 and Figure 7 for WE# and CE# controlled Program operation timing diagrams and Figure 21 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 2 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet Chip-Erase Operation The SST39VF320xB provide a Chip-Erase operation, which allows the user to erase the entire memory array to the "1" state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 6 for the command sequence, Figure 10 for timing diagram, and Figure 25 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. When WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence, WP# should be statically held high or low. `1'. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 8 for Data# Polling timing diagram and Figure 22 for a flowchart. Toggle Bits (DQ6 and DQ2) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating "1"s and "0"s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or CE#) pulse. DQ6 will be set to `1' if a Read operation is attempted on an Erase-Suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 1 shows detailed status bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or CE#) pulse of Write operation. See Figure 9 for Toggle Bit timing diagram and Figure 22 for a flowchart. TABLE 1: Write Operation Status Status Normal Standard Operation Program Standard Erase EraseSuspend Mode Read from Erase-Suspended Sector/Block Read from Non- Erase-Suspended Sector/Block Program Write Operation Status Detection The SST39VF320xB provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. DQ7 DQ7# 0 1 DQ6 Toggle Toggle 1 DQ2 No Toggle Toggle Toggle Data Data Data Data# Polling (DQ7) When the SST39VF320xB are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 s. During internal Erase operation, any attempt to read DQ7 will produce a `0'. Once the internal Erase operation is completed, DQ7 will produce a (c)2009 Silicon Storage Technology, Inc. DQ7# Toggle N/A T1.0 1384 Note: DQ7, DQ6 and DQ2 require a valid address when reading status information. S71384-01-000 1/09 3 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet Data Protection The SST39VF320xB provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Reset (RST#) The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode. When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place. See Figure 17. The Erase or Program operation that has been interrupted needs to be re-initiated after the device resumes normal operation mode to ensure data integrity. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Software Data Protection (SDP) The SST39VF320xB provide the JEDEC approved Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. These devices are shipped with the Software Data Protection permanently enabled. See Table 6 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value, during any SDP command sequence. Hardware Block Protection The SST39VF3202B support top hardware block protection, which protects the top 32 KWord block of the device. The SST39VF3201B support bottom hardware block protection, which protects the bottom 32 KWord block of the device. The Boot Block address ranges are described in Table 2. Program and Erase operations are prevented on the 32 KWord when WP# is low. If WP# is left floating, it is internally held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase operations on that block. TABLE 2: Boot Block Address Ranges Product Bottom Boot Block SST39VF3201B Top Boot Block SST39VF3202B 1F8000H-1FFFFFH T2.0 1384 Address Range 000000H-007FFFH Common Flash Memory Interface (CFI) The SST39VF320xB also contain the CFI information to describe the characteristics of the device. In order to enter the CFI Query mode, the system must write the three-byte sequence, same as product ID entry command with 98H (CFI Query command) to address 555H in the last byte sequence. The system can also enter the CFI Query mode, by using the one-byte sequence with 55H on Address and 98H on Data Bus. Once the device enters the CFI Query mode, the system can read CFI data at the addresses given in Tables 7 through 9. The system must write the CFI Exit command to return to Read mode from the CFI Query mode. (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 4 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet Product Identification The Product Identification mode identifies the devices as the SST39VF3201B and SST39VF3202B, and the manufacturer as SST. This mode may be accessed through software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 6 for software operation, Figure 13 for the Software ID Entry and Read timing diagram and Figure 23 for the Software ID Entry command sequence flowchart. TABLE 3: Product Identification Address Manufacturer's ID Device ID SST39VF3201B SST39VF3202B 0001H 0001H 235DH 235CH T3.0 1384 Security ID The SST39VF320xB devices offer a 136 word Security ID space. The Secure ID space is divided into two segments one factory programmed segment and one user programmed segment. The first segment is programmed and locked at SST with a random 128-bit number. The 128word user segment is left un-programmed for the customer to program as desired. To program the user segment of the Security ID, the user must use the Security ID Word-Program command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, neither Sec ID segment can be erased. The Secure ID space can be queried by executing a threebyte command sequence with Enter Sec ID command (88H) at address 555H in the last byte sequence. To exit this mode, the Exit Sec ID command should be executed. Refer to Table 6 for more details. Data BFH 0000H Product Identification Mode Exit/ CFI Mode Exit In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit/ CFI Exit command is ignored during an internal Program or Erase operation. See Table 6 for software command codes, Figure 15 for timing waveform, and Figure 23 and Figure 24 for flowcharts. (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 5 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet X-Decoder SuperFlash Memory Memory Address Address Buffer & Latches Y-Decoder CE# OE# WE# WP# RESET# Control Logic I/O Buffers and Data Latches DQ15 - DQ0 1384 B1.0 FIGURE 1: Functional Block Diagram A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RST# NC WP# NC A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Standard Pinout Top View Die Up 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 1384 48-tsop EK P1.0 FIGURE 2: Pin Assignments for 48-lead TSOP (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 6 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet TOP VIEW (balls facing down) 6 5 4 3 2 1 A13 A12 A14 A9 A8 A10 NC A15 A16 NC DQ15 VSS A11 DQ7 DQ14 DQ13 DQ6 A19 DQ5 DQ12 VDD DQ4 A20 DQ2 DQ10 DQ11 DQ3 A5 A1 DQ0 DQ8 DQ9 DQ1 A0 CE# OE# VSS WE# RST# NC WP# A18 A7 A3 A17 A4 A6 A2 ABCDEFGH 1384 4-tfbga B1K P2.0 FIGURE 3: pin assignments for 48-ball TFBGA TABLE 4: Pin Description Symbol AMS1-A0 Pin Name Address Inputs Functions To provide memory addresses. During Sector-Erase AMS-A11 address lines will select the sector. During Block-Erase AMS-A15 address lines will select the block. To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. To protect the top/bottom boot block from Erase/Program operation when grounded. To reset and return the device to Read mode. To activate the device when CE# is low. To gate the data output buffers. To control the Write operations. To provide power supply voltage: 2.7-3.6V Unconnected pins. T4.0 1384 DQ15-DQ0 Data Input/output WP# RST# CE# OE# WE# VDD VSS NC Write Protect Reset Chip Enable Output Enable Write Enable Power Supply Ground No Connection 1. AMS = Most significant address AMS = A20 for SST39VF320xB (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 7 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet TABLE 5: Operation Modes Selection Mode Read Program Erase Standby Write Inhibit Product Identification Software Mode VIL VIL VIH See Table 6 T5.0 1384 CE# VIL VIL VIL VIH X X OE# VIL VIH VIH X VIL X WE# VIH VIL VIL X X VIH DQ DOUT DIN X1 High Z High Z/ DOUT High Z/ DOUT Address AIN AIN Sector or block address, XXH for Chip-Erase X X X 1. X can be VIL or VIH, but no other value. (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 8 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet TABLE 6: Software Command Sequence Command Sequence Word-Program Sector-Erase Block-Erase Chip-Erase Erase-Suspend Erase-Resume Query Sec ID5 1st Bus Write Cycle Addr1 555H 555H 555H 555H XXXXH XXXXH 555H 555H 555H 555H 555H 55H 555H XXH Data2 AAH AAH AAH AAH B0H 30H AAH AAH AAH AAH AAH 98H AAH F0H 2nd Bus Write Cycle Addr1 2AAH 2AAH 2AAH 2AAH Data2 55H 55H 55H 55H 3rd Bus Write Cycle Addr1 555H 555H 555H 555H Data2 A0H 80H 80H 80H 4th Bus Write Cycle Addr1 WA3 555H 555H 555H Data2 Data AAH AAH AAH 5th Bus Write Cycle Addr1 2AAH 2AAH 2AAH Data2 55H 55H 55H 6th Bus Write Cycle Addr1 SAX4 BAX 4 Data2 50H 30H 10H 555H 2AAH 2AAH 2AAH 2AAH 2AAH 2AAH 55H 55H 55H 55H 55H 55H 555H 555H 555H 555H 555H 555H 88H A5H 85H 90H 98H F0H WA6 XXH6 Data 0000H User Security ID Word-Program User Security ID Program Lock-Out Software ID Entry7,8 CFI Query Entry CFI Query Entry Software ID Exit9,10 /CFI Exit/Sec ID Exit Software ID Exit9,10 /CFI Exit/Sec ID Exit T6.0 1384 1. Address format A10-A0 (Hex). Addresses A11- A20 can be VIL or VIH, but no other value, for Command sequence for SST39VF320xB. 2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence 3. WA = Program Word address 4. SAX for Sector-Erase; uses AMS-A11 address lines BAX, for Block-Erase; uses AMS-A15 address lines AMS = Most significant address AMS = A20 for SST39VF320xB 5. With AMS-A4 = 0; Sec ID is read with A3-A0, SST ID is read with A3 = 0 (Address range = 000000H to 000007H), User ID is read with A3 = 1 (Address range = 000008H to 000087H). Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0. 6. Valid Word-Addresses for Sec ID are from 000000H-000007H and 000008H to 000087H. 7. The device does not remain in Software Product ID Mode if powered down. 8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0, SST39VF3201B Device ID = 235DH, is read with A0 = 1, SST39VF3202B Device ID = 235CH, is read with A0 = 1. AMS = Most significant address AMS = A20 for SST39VF320xB 9. Both Software ID Exit operations are equivalent 10. If users never lock after programming, Sec ID can be programmed over the previously unprogrammed bits (data=1) using the Sec ID mode again (the programmed "0" bits cannot be reversed to "1"). Valid Word-Addresses for Sec ID are from 000000H-000007H and 000008H to 000087H. (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 9 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet TABLE 7: CFI Query Identification String1 for SST39VF320xB Address 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH Data 0051H 0052H 0059H 0002H 0000H 0000H 0000H 0000H 0000H 0000H 0000H Data Query Unique ASCII string "QRY" Primary OEM command set Address for Primary Extended Table Alternate OEM command set (00H = none exists) Address for Alternate OEM extended Table (00H = none exits) T7.0 1384 1. Refer to CFI publication 100 for more details. TABLE 8: System Interface Information for SST39VF320xB Address 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H Data 0027H 0036H 0000H 0000H 0003H 0000H 0004H 0005H 0001H 0000H 0001H 0001H Data VDD Min (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VDD Max (Program/Erase) DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts VPP min. (00H = no VPP pin) VPP max. (00H = no VPP pin) Typical time out for Word-Program 2N s (23 = 8 s) Typical time out for min. size buffer program 2N s (00H = not supported) Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms) Typical time out for Chip-Erase 2N ms (25 = 32 ms) Maximum time out for Word-Program 2N times typical (21 x 23 = 16 s) Maximum time out for buffer program 2N times typical Maximum time out for individual Sector/Block-Erase 2N times typical (21 x 24 = 32 ms) Maximum time out for Chip-Erase 2N times typical (21 x 25 = 64 ms) T8.0 1384 TABLE 9: Device Geometry Information for SST39VF320xB Address 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H Data 0016H 0001H 0000H 0000H 0000H 0002H 00FFH 0003H 0010H 0000H 003FH 0000H 0000H 0001H Data Device size = 2N Bytes (16H = 22; 222 = 4MByte) Flash Device Interface description; 0001H = x16-only asynchronous interface Maximum number of bytes in multi-byte write = 2N (00H = not supported) Number of Erase Sector/Block sizes supported by device Sector Information (y + 1 = Number of sectors; z x 256B = sector size) y = 1023 + 1 = 1024 sectors (03FFH = 1023) z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16) Block Information (y + 1 = Number of blocks; z x 256B = block size) y = 63 + 1 = 64 blocks (003FH = 63) z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256) T9.0 1384 (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 10 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 13.2V Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C for 10 seconds Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Outputs shorted for no more than one second. No more than one output shorted at a time. Operating Range Range Commercial Industrial Ambient Temp 0C to +70C -40C to +85C VDD 2.7-3.6V 2.7-3.6V AC Conditions of Test Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 19 and 20 Power Up Specifications All functionalities and DC specifications are specified for a VDD ramp rate of greater than 1V per 100 ms (0V to 3V in less than 300 ms). If the VDD ramp rate is slower than 1V per 100 ms, a hardware reset is required. The recommended VDD power-up to RESET# high time should be greater than 100 s to ensure a proper reset. TPU-READ > 100 s VDD 0V VIH VDD min RESET# TRHR > 50ns CE# 1384 F24.0 FIGURE 4: Power-Up Diagram (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 11 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet TABLE 10: DC Operating Characteristics VDD = 2.7-3.6V1 Limits Symbol IDD Parameter Power Supply Current Read3 Program and Erase ISB IALP ILI ILIW ILO VIL VILC VIH VIHC VOL VOH Standby VDD Current Auto Low Power Input Leakage Current Input Leakage Current on WP# pin and RST# Output Leakage Current Input Low Voltage Input Low Voltage (CMOS) Input High Voltage Input High Voltage (CMOS) Output Low Voltage Output High Voltage VDD-0.2 0.7VDD VDD-0.3 0.2 15 45 20 20 1 10 1 0.8 0.3 mA mA A A A A A V V V V V V Min Max Units Test Conditions Address input=VILT/VIHT2, at f=5 MHz, VDD=VDD Max CE#=VIL, OE#=WE#=VIH, all I/Os open CE#=WE#=VIL, OE#=VIH CE#=VIHC, VDD=VDD Max CE#=VILC, VDD=VDD Max All inputs=VSS or VDD, WE#=VIHC VIN=GND to VDD, VDD=VDD Max WP#=GND to VDD or RST#=GND to VDD VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max VDD=VDD Max VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min T10.0 1384 1. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25C (room temperature), and VDD = 3V. Not 100% tested. 2. See Figure 19 3. The IDD current listed is typically less than 2mA/MHz, with OE# at VIH. Typical VDD is 3V. TABLE 11: Recommended System Power-up Timings Symbol TPU-READ1 TPU-WRITE 1 Parameter Power-up to Read Operation Power-up to Program/Erase Operation Minimum 100 100 Units s s T11.0 1384 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 12: Capacitance (TA = 25C, f=1 Mhz, other pins open) Parameter CI/O1 CIN 1 Description I/O Pin Capacitance Input Capacitance Test Condition VI/O = 0V VIN = 0V Maximum 10 pF 10 pF T12.0 1384 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 13: Reliability Characteristics Symbol NEND TDR1 ILTH1 1,2 Parameter Endurance Data Retention Latch Up Minimum Specification 10,000 100 100 + IDD Units Cycles Years mA Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard 78 T13.0 1384 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a higher minimum specification. (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 12 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet AC CHARACTERISTICS TABLE 14: Read Cycle Timing Parameters VDD = 2.7-3.6V Symbol TRC TCE TAA TOE TCLZ1 TOLZ1 TCHZ1 TOHZ1 TOH1 TRP1 TRHR1 TRY1,2 Parameter Read Cycle Time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change RST# Pulse Width RST# High before Read RST# Pin Low to Read Mode 0 500 50 20 0 0 16 16 Min 70 70 70 35 Max Units ns ns ns ns ns ns ns ns ns ns ns s T14.0 1384 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. This parameter applies to Sector-Erase, Block-Erase, and Program operations. This parameter does not apply to Chip-Erase operations. TABLE 15: Program/Erase Cycle Timing Parameters Symbol TBP TAS TAH TCS TCH TOES TOEH TCP TWP TWPH TDS TDH1 TIDA TSE TBE TSCE 1 1 Parameter Word-Program Time Address Setup Time Address Hold Time WE# and CE# Setup Time WE# and CE# Hold Time OE# High Setup Time OE# High Hold Time CE# Pulse Width WE# Pulse Width WE# Pulse Width High CE# Pulse Width High Data Setup Time Data Hold Time Software ID Access and Exit Time Sector-Erase Block-Erase Chip-Erase Min 0 30 0 0 0 10 40 40 30 30 30 0 Max 10 Units s ns ns ns ns ns ns ns ns ns ns ns ns TCPH1 150 25 25 50 ns ms ms ms T15.0 1384 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 13 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet TRC ADDRESS AMS-0 TCE CE# TOE OE# VIH WE# TCLZ DQ15-0 HIGH-Z TOLZ TAA TOHZ TOH DATA VALID TCHZ DATA VALID HIGH-Z 1384 F03.0 Note: AMS = Most significant address AMS = A20 for SST39VF320xB FIGURE 5: Read Cycle Timing Diagram INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 555 TAH TWP WE# TAS OE# TCH CE# TCS DQ15-0 XXAA SW0 XX55 SW1 XXA0 SW2 DATA WORD (ADDR/DATA) TWPH TDS 2AA 555 ADDR TDH 1384 F04.0 Note: AMS = Most significant address AMS = A20 for SST39VF320xB WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence. X can be VIL or VIH, but no other value. FIGURE 6: WE# Controlled Program Cycle Timing Diagram (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 14 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet INTERNAL PROGRAM OPERATION STARTS TBP ADDRESS AMS-0 555 TAH TCP CE# TAS OE# TCH WE# TCS DQ15-0 XXAA SW0 XX55 SW1 XXA0 SW2 DATA WORD (ADDR/DATA) TCPH TDS 2AA 555 ADDR TDH 1384 F05.0 Note: AMS = Most significant address AMS = A20 for SST39VF320xB WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence. X can be VIL or VIH, but no other value. FIGURE 7: CE# Controlled Program Cycle Timing Diagram ADDRESS AMS-0 TCE CE# TOEH OE# TOE WE# TOES DQ7 DATA DATA# DATA# DATA 1384 F06.0 Note: AMS = Most significant address AMS = A20 for SST39VF320xB FIGURE 8: Data# Polling Timing Diagram (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 15 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet ADDRESS AMS-0 TCE CE# TOEH OE# TOE TOES WE# DQ6 and DQ2 TWO READ CYCLES WITH SAME OUTPUTS 1384 F07.0 Note: AMS = Most significant address AMS = A20 for SST39VF320xB FIGURE 9: Toggle Bits Timing Diagram SIX-BYTE CODE FOR CHIP-ERASE ADDRESS AMS-0 555 2AA 555 555 2AA 555 TSCE CE# OE# TWP WE# DQ15-0 XXAA SW0 XX55 SW1 XX80 SW2 XXAA SW3 XX55 SW4 XX10 SW5 1384 F08.0 Note: This device also supports CE# controlled Chip-Erase operation The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 15) AMS = Most significant address AMS = A20 for SST39VF320xB WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence. X can be VIL or VIH, but no other value. FIGURE 10: WE# Controlled Chip-Erase Timing Diagram (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 16 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet SIX-BYTE CODE FOR BLOCK-ERASE ADDRESS AMS-0 555 2AA 555 555 2AA BAX TBE CE# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX30 1384 F09.0 SW0 SW1 SW2 SW3 SW4 SW5 Note: This device also supports CE# controlled Block-Erase operation The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 15) BAX = Block Address AMS = Most significant address AMS = A20 for SST39VF320xB WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence. FIGURE 11: WE# Controlled Block-Erase Timing Diagram SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS AMS-0 555 2AA 555 555 2AA SAX TSE CE# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX50 1384 F10.0 SW0 SW1 SW2 SW3 SW4 SW5 Note: This device also supports CE# controlled Sector-Erase operation The WE# and CE# signals are interchangeable as long as minimum timings are met. (See Table 15) SAX = Sector Address AMS = Most significant address AMS = A20 for SST39VF320xB WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence. FIGURE 12: WE# Controlled Sector-Erase Timing Diagram (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 17 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet Three-Byte Sequence for Software ID Entry ADDRESS A14-0 555 2AA 555 0000 0001 CE# OE# TWP WE# TWPH DQ15-0 XXAA SW0 XX55 SW1 XX90 SW2 TAA 00BF Device ID 1384 F11.0 TIDA Note: Device ID = 235DH for SST39VF3201B and 235CH for SST39VF3202B WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence. X can be VIL or VIH, but no other value. FIGURE 13: Software ID Entry and Read Three-Byte Sequence for CFI Query Entry ADDRESS A14-0 555 2AA 555 CE# OE# TWP WE# TWPH DQ15-0 XXAA SW0 XX55 SW1 XX98 1384 F12.0 TIDA TAA SW2 Note: WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence. X can be VIL or VIH, but no other value. FIGURE 14: CFI Query Entry and Read (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 18 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET ADDRESS A14-0 555 2AA 555 DQ15-0 XXAA XX55 XXF0 TIDA CE# OE# TWP WE# TWHP SW0 SW1 SW2 1384 F13.0 Note: WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence. X can be VIL or VIH, but no other value. FIGURE 15: Software ID Exit/CFI Exit THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY ADDRESS AMS-0 555 2AA 555 CE# OE# TWP WE# TWPH DQ15-0 XXAA SW0 XX55 SW1 XX88 SW2 1384 F14.0 TIDA TAA Note: AMS = Most significant address AMS = A20 for SST39VF320xB WP# must be held in proper logic state (VIL or VIH) 1 s prior to and 1 s after the command sequence. X can be VIL or VIH, but no other value. FIGURE 16: Sec ID Entry (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 19 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet TRP RST# CE#/OE# TRHR 1384 F15.0 FIGURE 17: RST# Timing Diagram (When no internal operation is in progress) TRP RST# TRY CE#/OE# End-of-Write Detection (Toggle-Bit) 1384 F16.0 FIGURE 18: RST# Timing Diagram (During Program or Erase operation) (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 20 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1384 F17.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 19: AC Input/Output Reference Waveforms TO TESTER TO DUT CL 1384 F18.0 FIGURE 20: A Test Load Example (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 21 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet Start Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XXA0H Address: 555H Load Word Address/Word Data Wait for end of Program (TBP,? Data# Polling bit, or Toggle bit operation) Program Completed X can be VIL or VIH, but no other value 1384 F19.0 FIGURE 21: Word-Program Algorithm (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 22 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet Internal Timer Program/Erase Initiated Toggle Bit Program/Erase Initiated Data# Polling Program/Erase Initiated Wait TBP, TSCE, TSE or TBE Read word Read DQ7 Program/Erase Completed Read same word No Is DQ7 = true data? Yes No Does DQ6 match? Yes Program/Erase Completed Program/Erase Completed 1384 F20.0 FIGURE 22: Wait Options (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 23 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet CFI Query Entry Command Sequence Sec ID Query Entry Command Sequence Software Product ID Entry Command Sequence Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX98H Address: 55H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Wait TIDA Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX98H Address: 555H Read CFI data Load data: XX88H Address: 555H Load data: XX90H Address: 555H Wait TIDA Wait TIDA Wait TIDA Read CFI data Read Sec ID Read Software ID X can be VIL or VIH, but no other value 1384 F21.0 FIGURE 23: Software ID/CFI Entry Command Flowcharts (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 24 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet Software ID Exit/CFI Exit/Sec ID Exit Command Sequence Load data: XXAAH Address: 555H Load data: XXF0H Address: XXH Load data: XX55H Address: 2AAH Wait TIDA Load data: XXF0H Address: 555H Return to normal operation Wait TIDA Return to normal operation X can be VIL or VIH, but no other value 1384 F22.0 FIGURE 24: Software ID/CFI Exit Command Flowcharts (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 25 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet Chip-Erase Command Sequence Load data: XXAAH Address: 555H Sector-Erase Command Sequence Load data: XXAAH Address: 555H Block-Erase Command Sequence Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX80H Address: 555H Load data: XX80H Address: 555H Load data: XX80H Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XXAAH Address: 555H Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX55H Address: 2AAH Load data: XX10H Address: 555H Load data: XX50H Address: SAX Load data: XX30H Address: BAX Wait TSCE Wait TSE Wait TBE Chip erased to FFFFH Sector erased to FFFFH Block erased to FFFFH X can be VIL or VIH, but no other value 1384 F23.0 FIGURE 25: Erase Command Sequence (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 26 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet PRODUCT ORDERING INFORMATION SST 39 XX VF 320 2B XX XXX XB 70 XX 4C XX EK E XX X Environmental Attribute E1 = non-Pb Package Modifier K = 48 balls or leads Package Type E = TSOP (type1, die up, 12mm x 20mm) B3 = TFBGA (6mm x 8mm, 0.8mm pitch) Temperature Range C = Commercial = 0C to +70C I = Industrial = -40C to +85C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns Hardware Block Protection 1 = Bottom Boot-Block 2 = Top Boot-Block Device Density 320= 32Mbit Voltage V = 2.7-3.6V Product Series 39 = Multi-Purpose Flash Plus 1. Environmental suffix "E" denotes non-Pb solder. SST non-Pb solder devices are "RoHS Compliant". Valid Combinations for SST39VF3201B SST39VF3201B-70-4C-EKE SST39VF3201B-70-4I-EKE SST39VF3201B-70-4C-B3KE SST39VF3201B-70-4I-B3KE Valid Combinations for SST39VF3202B SST39VF3202B-70-4C-EKE SST39VF3202B-70-4I-EKE SST39VF3202B-70-4C-B3KE SST39VF3202B-70-4I-B3KE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 27 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet PACKAGING DIAGRAMS 1.05 0.95 Pin # 1 Identifier 0.50 BSC 12.20 11.80 0.27 0.17 18.50 18.30 0.15 0.05 DETAIL 1.20 max. 0.70 0.50 20.20 19.80 0- 5 Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 0.70 0.50 1mm 48-tsop-EK-8 FIGURE 26: 48-lead Thin Small Outline Package (TSOP) 12mm x 20mm, SST Package Code: EK (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 28 32 Mbit Multi-Purpose Flash Plus SST39VF3201B / SST39VF3202B Data Sheet TOP VIEW 8.00 0.20 BOTTOM VIEW 5.60 0.80 0.45 0.05 (48X) 6 5 4 3 2 1 0.80 ABCDEFGH A1 CORNER HGFEDCBA 4.00 6.00 0.20 6 5 4 3 2 1 SIDE VIEW 1.10 0.10 A1 CORNER SEATING PLANE 0.35 0.05 0.12 1mm Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size is 0.38 mm ( 0.05 mm) 48-tfbga-B3K-6x8-450mic-4 FIGURE 27: 48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm, SST Package Code: B3K TABLE 16: Revision History Number 00 01 Description Date Mar 2008 Jan 2009 * * * Initial release Changed 1V per 100 s to 1V per 100 ms in Power Up Specifications on page 11 Changed status from Preliminary Specifications to Data Sheet Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com (c)2009 Silicon Storage Technology, Inc. S71384-01-000 1/09 29 |
Price & Availability of SST39VF3201B-70-4C-B3KE
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